Generally, heteroepitaxy means epitaxially growing on a crystal material another crystal material, e.g. epitaxially growing germanium (Ge) or group III/V compound semiconductors, etc. on a silicon (Si) substrate. With the continuous development of the semiconductor technology, the heteroepitaxy technology is becoming more and more important. For example, a high-performance Ge-channel Metal Oxide Semiconductor Field Effect Transistor (MOSFET) can be formed by depositing Ge having high carrier mobility as a channel material on a Si substrate. Further, it is possible to facilitate the integration of optoelectronic devices with the Si Complementary Metal Oxide Semiconductor (CMOS) technology by depositing a group III/V compound semiconductor material and the like, for example, on a Si substrate.
However, the lattices of the two crystal materials generally do not match, causing defects such as dislocations during the growth. For example, epitaxially growing more than a few nanometers (nm) of Ge directly on Si can lead to a dislocation density of 108-109/cm2 due to the lattice mismatch of 4.2% between the two materials. Such defects have negative impacts on the grown crystal and thus a resulting device.
Currently, various methods have been proposed to reduce such defects occurring in heteroepitaxy, e.g. the graded buffer technology, the post-growth high-temperature annealing technology, and the Aspect Ratio Trapping (ART) technology, etc. FIG. 1 is a schematic diagram showing how to reduce the defects by ART. As shown in FIG. 1, a dielectric material (e.g. SiO2) 110 is disposed on a Si substrate 100. The dielectric material 110 has openings with a relatively large Aspect Ratio (AR) defined therein. Then a Ge layer 120, for example, is epitaxially grown on the Si substrate 100. It has been found that defects occurring during the growth such as dislocations are approximately perpendicular to the growing surface. Since the size of the openings defined in the dielectric material 110 is relatively small, the grown Ge material generally has a profile where a middle portion is relative high and side portions are relative low in the respective openings. Namely, the growing surface is not parallel to the substrate surface, so the defects 130 extend upward in oblique directions as shown in FIG. 1. Finally, these defects terminate at the non-crystal dielectric material 110 and thus are prevented from further extending upward.
In other words, during the epitaxial growth, although most of the defects are confined at bottom portions of the openings, the defects still exist. Furthermore, when the semiconductor materials, which are respectively epitaxially grown in adjacent openings, coalesce above the dielectric material 110, coalescence dislocations 140 will occur.
Also, it is known that a SOI (Silicon-On-Insulator) structure helps to improve device performances in many applications. A conventional SOI structure is a semiconductor (e.g. Si)—insulator (e.g. silicon oxide)—semiconductor (e.g. Si) structure, for example. This structure is generally formed by oxidizing surfaces of two separate Si chips respectively, and combining the two Si chips in such a way that the oxidized surfaces face each other. However, there is not an effective process for incorporating the SOI technique in a heterogeneous semiconductor structure, which includes two layers of different semiconductor materials.